US Patent 7429526 Method of forming silicide gate with interlayer
Patent 7429526 was granted and assigned to Xilinx on September, 2008 by the United States Patent and Trademark Office.
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A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.
US Patent 07429526 Method of forming silicide gate with interlayer US Patent 7429526 Method of forming silicide gate with interlayer
US Patent 07429526 Method of forming silicide gate with interlayer
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