US Patent 7405124 Fabricating method of non-volatile memory
Patent 7405124 was granted and assigned to Powerchip Semiconductor on July, 2008 by the United States Patent and Trademark Office.
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A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the first mask layers are patterned to form openings exposing part of the surface of the substrate and the isolation structures. A tunneling dielectric layer and a first conductive layer are formed on the substrate. The first conductive layer is filled in the opening, and is divided into blocks by the isolation structures, the second mask layer, and the first mask layer. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the substrate to fill up the openings. Doped regions are formed in the substrate on both sides of the second conductive layer.
US Patent 07405124 Fabricating method of non-volatile memory US Patent 7405124 Fabricating method of non-volatile memory
US Patent 07405124 Fabricating method of non-volatile memory
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