Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Rajiv V. Joshi0
Yuen H. Chan0
Donald W. Plass0
Date of Patent
July 22, 2008
0Patent Application Number
117822820
Date Filed
July 24, 2007
0Patent Primary Examiner
Patent abstract
A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
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