US Patent 7388777 Semiconductor device

A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS•FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS•FET for writing data, a MIS•FET for reading data, and a capacitance section. Gate electrodes of the MIS•FETs and a capacitance electrode of the capacitance section are constituted of part of the same floating gate electrode. A control gate electrode of the nonvolatile memory cell is formed of part of an n well to which the capacitance electrode is opposite.