US Patent 7385245 Low power memory subsystem with progressive non-volatility

The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells of each array has a tunnel layer under an embedded trap layer. Each array has memory cells with a different tunnel layer thickness to change the read/write speeds and charge retention times for that array.