US Patent 7382675 Semiconductor memory device

According to an aspect of the invention, there is provided a semiconductor memory device including a first power source which generates a first power supply voltage, a second power source which generates a second power supply voltage, a generation circuit which generates a third power supply voltage from the first power supply voltage, a switching circuit which selects one of the second power supply voltage and the third power supply voltage, and a fuse circuit connected to the switching circuit and equipped with a fuse element to carry out a fuse reading operation, wherein the third power supply voltage is supplied from the switching circuit to the fuse circuit during the fuse reading operation.