Patent attributes
A switched distributed power amplifier includes an amplifier stage that includes a first amplifier subsection and a second amplifier subsection, both including one or more field effect transistors (FETs). Each FET in the first amplifier subsection is coupled to a radio frequency (RF) input terminal. Each FET in the second amplifier subsection is coupled to the RF input terminal through an input delay element, which includes a first inductor, a first capacitance associated with gates of the FETs in the first amplifier subsection, a second capacitance associated with gates of the FETs in the second amplifier subsection, and a third capacitance associated with a capacitor coupled to the RF input terminal. The input delay element is designed such that the sum of the first and third capacitances is equal to the second capacitance. A shunt switch prevents the second amplifier subsection from turning on during a low power mode.
