US Patent 7375565 Delay locked loop in semiconductor memory device

A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively comparing a phase of a delayed feedback signal and a phase of the feedback signal with a phase of the external clock signal; a clock selecting block for selecting one of the first and second internal clock signals based on one comparison result to thereby generate a selected internal clock signal; a stuck checking block for determining a delay value based on the other comparison result; a delay line block for delaying the selected internal clock signal by the delay value; and an output buffer for buffering an outputted signal from the delay line block to thereby generating a DLL clock signal.