US Patent 7372752 Test mode controller

A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate a reset signal and a control signal generating block for receiving a plurality of input signals activated in a wafer burn-in test to generate a plurality of test control signals in response to the reset signal and a programmable test signal activated in a programmable stress test.