US Patent 7365357 Strain inducing multi-layer cap

A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.