Patent attributes
At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit than the complete cell array. The signal control unit disposed on one-end side of a row of the cell arrays receives/outputs a signal from/to a global line. A read/write control unit disposed between the cell arrays controls data read/write from/to the cell arrays. The global line extends from one-end side of the row of the cell arrays to be connected to the read/write control unit. The global line is always wired on the short incomplete cell array, thereby reducing load capacitance and charge/discharge current thereof. This can reduce power consumption of a semiconductor memory, and shorten the access time thereof.
