US Patent 7352314 Digital-to-analog converter circuit

Data of a zeroth bit is supplied via a charge control transistor for the zeroth bit to a corresponding capacitor, data of a first bit is supplied via a charge control transistor for the first bit to a corresponding capacitor, and data of a second bit is supplied via a charge control transistor for the second bit to a corresponding capacitor. The capacitors for the zeroth bit, first bit, and second bit have capacitances which are set in a ratio of 1:2:4 and capabilities of the corresponding charge control transistors for respective bits are set in a ratio of 1:2:4. With this structure, charging of capacitors corresponding to the bits can be performed under similar conditions.