US Patent 7349283 Integrated semiconductor memory

An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects. Comparator circuits are arranged at locations along the respective interconnects, but preferably at the end of each interconnect. The comparator circuits compare a voltage level on the interconnects with a level of a reference voltage. In a manner dependent on the level comparison, the test mode control circuit generates evaluation signals at contact pads. The reference voltage is fed in via a monitor pad. Using the contact pads, which are generally formed with a large area, the evaluation signals can easily be tapped off by a tester.