Patent attributes
A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable to couple between the second node and the predetermined node, and a control circuit configured to subject one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, wherein the MIS transistors of the latch have a lightly-doped-drain structure that includes first diffusion regions having a first impurity concentration and second diffusion regions having a second impurity concentration smaller than the first impurity concentration, and each of the first MIS transistor and the second MIS transistor has a doped diffusion region closest to a conduction channel with an impurity concentration different from the second impurity concentration.
