Patent attributes
A domain crossing device for use in a semiconductor memory device, including: a unit for comparing a phase of an internal clock signal with a phase of a delay locked loop (DLL) clock signal to generate a first clock selection signal and a phase detection period signal in response to a detection starting signal and a second clock selection signal; a unit for generating a plurality of initial latency signals in response to the phase detection period signal, the detection starting signal and a column address strobe (CAS) latency signal; a unit for receiving the plurality of initial latency signals and the detection starting signal to generate a plurality of latency signals, a clock selection signal and the second clock selection signal; and a unit for generating the detection starting signal based on a self refresh signal, a power-up signal and a DLL disable signal.
