US Patent 7336541 NAND flash memory cell programming

A flash memory device, such as a NAND flash, is included having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are included.