US Patent 7335943 Ultrascalable vertical MOS transistor with planar contacts

A doped silicon block or island, formed above a drain electrode in substrate of a die or chip, has a height corresponding to the desired length of a channel. A source electrode is formed above the silicon island and allows for contact from above. Contact from above may also be made with an L-shaped control gate and with the subsurface drain. A horizontal array of contacts for source, gate and drain is formed for the vertical transistor that is built. If a layer of nanocrystals is incorporated into a layer between the gate and the channel, a non-volatile floating gate transistor may be formed. Without the layer of nanocrystals, an MOS or CMOS transistor is formed.