US Patent 7335936 DRAM memory having vertically arranged selection transistors

Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an outer electrode, a dielectric layer being arranged between the inner and the outer electrodes, a vertical selection transistor that has a substantially perpendicular channel region, which is constructed adjacent to an upper region of the trench hole and which connects the inner electrode of the trench capacitor to a bit line, it being possible to construct a conductive channel as a function of the potential of a word line in the channel region, the channel region partially enclosing the trench hole in its upper region, and the associated work line at least partially surrounding the channel region.