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US Patent 7333580 Pipelined parallel processing of feedback loops in a digital circuit

Patent 7333580 was granted and assigned to Broadcom (company) on February, 2008 by the United States Patent and Trademark Office.

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Current Assignee
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
73335801
Patent Inventor Names
Keshab K Parhi1
Date of Patent
February 19, 2008
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Patent Application Number
101470491
Date Filed
May 17, 2002
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Patent Primary Examiner
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Young T. Tse
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Patent abstract

Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

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