Patent attributes
The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection transistor T1 and a MOS memory transistor T2 connected in series between a voltage supply line BL and ground Gnd. The device further comprises programming means for applying predetermined voltages Vsel, Vctrl, Vprog to the gate of the selection transistor T1, to the gate of the memory transistor T2 and to the voltage supply line BL. The applied voltages Vsel, Vctrl, Vprog are selected such that they force the memory transistor T2 into a snap-back mode resulting in a current thermally damaging the drain junction of the memory transistor T2. The invention relates equally to a corresponding method for programming a one time programmable memory.
