US Patent 7324383 Selective slow programming convergence in a flash memory device

A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.