US Patent 7313745 Decoder for pin-based scan test

An integrated circuit design block includes combinational and sequential logic defining core logic of the integrated circuit design block, and boundary logic defined at an outer region of the integrated circuit design block. The integrated circuit design block also includes a control test unit that has a scan chain decoder and a boundary scan decoder. The scan chain decoder includes scan chain select circuitry for enabling the scan chain decoder during scan testing of the core logic. The scan chain select circuitry further includes a pin for disabling the scan chain decoder during testing of the boundary logic. The scan chain decoder is limited to share pins defined by the boundary scan decoder, and is both 4-pin and 5-pin IEEE 1149.1 compliant.