Patent attributes
N data bits are stored in ┌N/M┐ cells by programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies one of the following criteria: Either the number of threshold voltage comparisons needed to read all M bits sequentially is at most 1 more than the smallest such number, or the largest number of threshold voltage comparisons needed to read any bit is minimized, or the smallest number of threshold voltage comparisons needed to read any bit is minimized, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit statically is at most 1 more than the smallest such difference, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit dynamically is minimized.
