Patent attributes
A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The isolation layers are disposed between the control gates and the doping regions, and the isolation structures are disposed within the substrate where the doped regions and the control gates do not overlap. Furthermore, the floating gates are disposed between the control gates and the substrate that is not covered by the isolation layers. The tunneling dielectric layers are disposed between the substrate and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.
