Patent attributes
In the two-stage conversion type of digital-to-analog converter, the m most significant bits in a digital signal are provided to a first-stage selector, selecting a pair of adjacent lower and upper limit voltages among 2m+1 different stepwise voltages generated by a resistive voltage divider. The resistors divide the voltage between the lower and upper limits into different divided voltages. A second-stage selector selects corresponding one of the divided voltages according to two least significant bits in the digital signal. When the digital signal changes, a load signal is provided for a predetermined time period, allowing switches to short-circuit respective component resistors. The output of the second-stage selector is thus quickly charged to the upper limit voltage when the digital signal changes. When the load signal subsequently stops, the normal divided voltage is generated, providing the target output voltage. Thus, the conversion accuracy and response speed are improved.
