US Patent 7283388 Memory device using multiple layer nano tube cell

A memory device features a multiple layer nano tube cell. In the memory device, a cross point cell array including a capacitor and a PNPN nano tube switch is effectively arranged to reduce the whole memory size. Also, in the memory device, the nano tube cell array including a capacitor and a PNPN nano tube switch which does not require an additional gate control signal is positioned on a circuit device region including a word line driving unit, a sense amplifier, a data bus, a main amplifier, a data buffer and an input/output port, and an interlayer insulating film is interposed between a cell array region and the circuit device region.