Patent attributes
A power-on reset circuit is provided. The power-on reset circuit includes an adjusting circuit, a charging/discharging unit and an output circuit. The adjusting circuit receives and adjusts a clock signal so as to output a control signal, wherein a minimum level of the control signal is clamped to be higher than a pre-defined level. The charging/discharging unit having a capacitor apparatus receives the control signal, determines whether to charge/discharge the capacitor apparatus based on the control signal, and outputs a storage voltage of the capacitor apparatus. The output circuit receives the storage voltage and outputs the reset signal. Wherein, the adjusting circuit determines the charging/discharging duty cycle of the charging/discharging unit by adjusting the waveform and the minimum level of the control signal. The output circuit enables/disables the reset signal according to whether the storage voltage reaches the threshold voltage of the output circuit.
