US Patent 7271664 Phase locked loop circuit

A phase locked loop circuit (PLL) has a reference terminal for receiving a reference signal and an output terminal for providing an output signal. The PLL comprises a phase comparator having first and second inputs and having an output at which it provides a signal that depends on phase difference between signals received at the first and second inputs respectively, a voltage controlled oscillator (VCO) having a control input coupled to the output of the phase comparator and having an output coupled to the output terminal of the PLL, the VCO generating an output signal having a frequency that depends on the voltage of a signal received at the control input of the VCO, a feedback path coupled to the output of the VCO for providing a feedback signal, and a bitstream generator for generating first and second pseudo random bitstreams (PRBSs) in response to the reference signal and the feedback signal respectively and applying the first and second PRBSs to the first and second inputs respectively of the phase comparator.