Patent attributes
A fast-settling digital automatic gain control circuit comprises first and second gain-controllable amplifiers in series. Each amplifier can be digitally switched between minimum and maximum gains by control logic that receives inputs from a multi-level voltage comparator. A peak detector connected to the output of the first gain-controlled amplifier is used to set the overall operating ranges for several threshold detectors. Four reference voltages are generated from the peak detector. The highest reference voltage is used to clock and reset the gain control logic with a hysteresis comparator to the instantaneous input signal from the first gain-controlled amplifier. The three other lower reference voltages are used to provide three-bits of digital input data to the gain control logic. Two digital controls are output, a min/max gain bit for the first gain-controlled amplifier, and a similar min/max gain bit for the second gain-controlled amplifier.
