US Patent 7265006 Method of fabricating heterojunction devices integrated with CMOS

A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to contact individually each one of a plurality of heterojunction devices or contact a plurality of heterojunction devices in parallel. This method can be used to fabricate three-terminal devices and vertically stacked devices.