US Patent 7256458 Doubly asymmetric double gate transistor structure

The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions. This asymmetric structure allows for the performance benefits of a double gate design without the increased capacitance that would normally result.