Patent attributes
A decoder circuit includes a first delay means for delaying unit data read out from a dictionary, a selecting means for selecting data and a second delay means for delaying data selected by the selecting means, wherein delayed data from the second selecting means is written again in the dictionary, the selecting means is supplied with delayed data from the first delay means and delayed data from the second delay means and the selecting means selects delayed data from the second delay means if a read address and a write address of the dictionary fall within a range of a predetermined distance corresponding to delay amounts of the first and second delay means and the selecting means selects delayed data from the first delay means in other cases.
