Patent attributes
A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage corresponding to the variation of an output from the preamplifier during the sampling period and holds the voltage corresponding to the output from the preamplifier during the hold period initiated by a transition of a clock signal, and a current switching circuit which is connected to the output pin of the preamplifier and enables the current flowing into the first transistor within the preamplifier during the sampling period to flow into another second transistor to apply a constant potential as an input to the core section.
