US Patent 7237162 Deterministic BIST architecture tolerant of uncertain scan chain outputs
Patent 7237162 was granted and assigned to Synopsys on June, 2007 by the United States Patent and Trademark Office.
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A BIST architecture that allows efficient compression and application of deterministic ATPG patterns while tolerating uncertain bits is provided. In accordance with one feature of the invention, a large number of short scan chains can be configured between a decompressor and an observe selector. The observe selector selectively presents values of specific scan chains or scan cells to an external tester, thereby significantly reducing test data and test cycles. Advantageously, the core of the tested device is not changed as would be the case in BIST architectures including MISRs. Moreover, test points or logic to block uncertain bits do not need to be inserted. Furthermore, the loaded care bits for the scan chains as well as the bits for controlling the observe selector can be deterministically controlled, thereby providing optimal testing flexibility.
US Patent 07237162 Deterministic BIST architecture tolerant of uncertain scan chain outputs US Patent 7237162 Deterministic BIST architecture tolerant of uncertain scan chain outputs
US Patent 07237162 Deterministic BIST architecture tolerant of uncertain scan chain outputs
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