US Patent 7203123 Integrated DRAM memory device

An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and bitlines, wherein the number of memory blocks including a first set of memory blocks the memory cells thereof having a first random access time and a second set of memory blocks the memory cells thereof having a second random access time, wherein the second random access time is smaller that the first random access time.