US Patent 7198994 Semiconductor device and manufacturing method of semiconductor device

Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate, grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.