US Patent 7193270 Semiconductor device with a vertical transistor
Patent 7193270 was granted and assigned to Renesas Technology Corp on March, 2007 by the United States Patent and Trademark Office.
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A semiconductor device which, even when a vertical transistor is adopted, is able to prevent a product yield from decreasing and performance from deteriorating, and at the same time, to achieve high-density integration of chips and high performance. The semiconductor device includes: a semiconductor substrate; a tower-like gate pillar formed on the semiconductor substrate via an insulation layer and including a channel region formed so as to be positioned between impurity diffusion regions in a vertically extended direction with respect to a principal side of the substrate; a gate insulation film formed on an outer surface of the gate pillar; and a gate electrode film including multiple conductive layers formed on an outer surface of the gate insulation film.
US Patent 07193270 Semiconductor device with a vertical transistor US Patent 7193270 Semiconductor device with a vertical transistor
US Patent 07193270 Semiconductor device with a vertical transistor
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