Patent attributes
Disclosed is a PDP driving circuit and a driving method thereof. A first switch is coupled between a Y electrode of a panel capacitor and a positive polarity terminal of a voltage source supplying a voltage Vs/2, a second switch is coupled between the positive polarity terminal of the voltage source and ground, a third switch is coupled between the Y electrode and a negative polarity of the voltage source, and a fourth switch is coupled between the negative polarity of the voltage source and ground. The voltage −Vs/2 is applied to an X electrode of the panel capacitor while the voltage Vs/2 is applied to the Y electrode thereof, and the voltage Vs/2 is applied to the X electrode while the voltage −Vs/2 is applied to the Y electrode.