US Patent 7176433 Resolution enhancement for macro wafer inspection

A method and apparatus for improving system resolution for a defect line scanner while not increasing aliasing effects, or alternatively to maintain system resolution for a defect scanner while decreasing aliasing effects. This is accomplished by decreasing effective pixel size for a CCD array defect line scanner while not decreasing signal-to-noise ratio, with minimal changes to the current machine. The method utilizes a sampling phase shift between successive lines of a multi-line sensor array during scanning.