US Patent 7173469 Clocking system and method for a memory

A clocking system for a memory that accomplishes these and other objectives has an external clock. A clock shaper has an input coupled to the external clock and an access clock at an output. A first delay block has an input coupled to the external clock and an output coupled to a master of an output register. A slave of the output register is coupled to the external clock. By having the master clock trailing the slave clock a temporary transparency window condition is created at the output register, allowing an improved cycle time (speed) prime bin distribution.