Patent attributes
A window via capacitor comprises a stacked multilayer configuration of at least one bottom layer, a plurality of first and second layers, a transition layer and a cover layer. An alternative window via capacitor comprises a stacked configuration of a bottom window layer, a bottom transition layer, a plurality of first and second layers, followed by a top window layer and a top cover layer. Each first and second layer is preferably characterized by a sheet of dielectric material with a respective first or second electrode plate provided thereon. Adjacent first and second electrode plates form opposing active capacitor plates in the multilayer configuration. Portions of each first and second electrode plate extend to and are exposed on selected side portions of the periphery of the window via capacitor. Electrode portions of each transition layer are aligned in respective similar locations to the first and second electrode plates such that peripheral terminations can connect selected electrode portions of a first polarity together and selected portions of the opposing polarity together. In some embodiments, the connection of peripheral terminations to the electrode portions of the transition layer collect the two opposing terminations onto a single planar surface. Window vias may then be formed through windows provided in the cover layers to effect low inductance electrical connection to the active components of the window via capacitor. Solder balls may also be applied to such window vias to yield a capacitor compatible with BGA mounting technology.
