US Patent 7170439 Self-calibration circuit for capacitance mismatch

A self-calibration circuit for capacitance mismatch is provided. The circuit comprises a sample-and-hold (S/H) circuit, a comparator, and a switch control circuit. The S/H circuit comprises a compensation capacitor array, a target capacitor, and a reference capacitor. The S/H circuit provides an output voltage, wherein the output voltage is an operation result based on the capacitance of the target capacitor and the reference capacitor, and the equivalent capacitance of the compensation capacitor array. The comparator provides a comparison signal according to whether the output voltage of the S/H circuit is positive or negative. The switch control circuit controls the equivalent capacitance of the array according to the comparison signal such that the result of the target capacitance added to the equivalent capacitance of the array gradually approximates the reference capacitance with each cycle of a clock signal.