Patent attributes
An apparatus for digital-to-analog conversion and the method thereof is disclosed, wherein the complete scale-tuned levels of more bits may be presented with an output of less bits. The apparatus comprises a timing controller, a scale-tuned circuit and a digital-to-analog converter. The timing controller receives an a-bit grayscale value, and outputs a selection signal and a b-bit control signal, wherein a, b are both positive integers and a>b>=1. The selection signal has two states: if the grayscale value is less than or equal to 2a−2c, wherein c is equal to a−b, the selection signal is in a first state; and if the grayscale value is equal to 2a−2c+n, wherein n is an integer and 0<n<2c, the selection signal has a probability of n/2c to be in a second state, and has a probability of 1−n/2c to be in the first state.
