US Patent 7167016 Operation mode setting circuit

According to the present invention, there is provided an operation mode setting circuit comprising:a plurality of latch circuits each of which receives one of at least two bits contained in an operation mode setting signal for setting an operation mode, and latches and outputs the bit in synchronism with a clock;an inverter which inverts at least one of output signals from said latch circuits; anda logic circuit which receives the output signals from said latch circuits and the signal inverted by said inverter, performs a predetermined logic operation, and outputs a result.