Patent attributes
In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.
