Patent 7158532 was granted and assigned to Intel on January, 2007 by the United States Patent and Trademark Office.
Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transaction, such as an isochronous memory read or write, is scheduled in a service period N if the isochronous transaction is ready to be serviced before service period N at the first or second device. An asynchronous transaction ready to be serviced at the first or second device, such as an asynchronous memory read or write, is scheduled if no isochronous transaction is ready to be serviced. The asynchronous transaction may be scheduled by (a) scheduling an asynchronous transaction ready to be serviced at the first device if no asynchronous transaction is ready to be serviced at the second device; (b) scheduling an asynchronous transaction ready to be serviced at the second device if no asynchronous transaction is ready to be serviced at the first device; and (c) scheduling an asynchronous transaction ready to be serviced at the first or second device, according to an arbitration algorithm, if asynchronous transactions are ready to be serviced at both the first device and the second device. The amount of buffer space available in the first or second device may also be used to schedule asynchronous transactions.