US Patent 7151699 Semiconductor memory device

Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from being occurred. The semiconductor memory device, which comprises a data inputting block 30 for transferring data applied to a plurality of data input/output pins DQ0 to DQ15 to a plurality of global I/O buses gio<0:15>, a data multiplexing block 32 for multiplexing the data carried on the plurality of global I/O buses gio<0:15> according to a data width option, and a main write driver 34, in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.