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US Patent 7138311 Semiconductor integrated circuit device and manufacture method therefore

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Patent

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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7138311
Patent Inventor Names
Akio Kitamura0
Date of Patent
November 21, 2006
Patent Application Number
10869811
Date Filed
June 16, 2004
Patent Primary Examiner
‌
Edward Wojciechowicz
Patent abstract

A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.

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