Patent attributes
A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second potential value being smaller than said first potential value, and means for their switching between states exhibiting different electric resistance values. The memory cell includes a first field effect transistor and a second field effect transistor, said first and second transistors having drain-source-paths and gate electrodes, said drain-source-paths of said first and second transistors being connected in a second series connection and being connected to at least one of first current lines. The first current line is connected to a potential value level detector for sensing a potential difference as to said third potential value.
