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US Patent 7129507 Chip mis-position detection method

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Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
71295071
Patent Inventor Names
Yutaka Ueda1
Konosuke Murakami1
Takashi Ishimoto1
Yoshio Niki1
Akira Yamamoto1
Date of Patent
October 31, 2006
1
Patent Application Number
110510351
Date Filed
February 4, 2005
1
Patent Primary Examiner
‌
Stephone B. Allen
1
Patent abstract

The invention is a method for detecting float or peel of semiconductor chips arranged in X and Y axes directions diced and bonded to a dicing tape on a stage. The method includes detecting float or peel of the semiconductor chips in a respective horizontal or longitudinal row arranged in the X or Y axis direction; moving the stage in the X axis direction, the Y axis direction, a Z axis direction, and a rotational direction around the Z axis for aligning the stage with a position detection unit for detecting positions of the semiconductor chips in the X axis direction and the Y axis direction; detecting the positions of abnormal semiconductor chips in the respective horizontal or longitudinal row that includes said abnormal semiconductor chips; and specifying the positions of said abnormal semiconductor chips on the X-Y axes.

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